Mr. Tech Dweeb Tech Tip Archive

Bare Board Fabrication

Today's typical basic drill geometry incorporates a 15 degree primary angle, a 30 degree secondary angle, a high helix, polished flutes, relieved margins, a back tapered body , and a fine grain tungsten carbide base.

Although customer specifications vary, typical coating thickness are shown in the table below.

Coating Thickness (microinches)

HASL 200 to 300 µin

ENIG 100 to 250 µin of nickel 3 to 10 µin of gold

Tab nickel/gold* 100 µin of electroplated nickel
30 to 50 µin of electroplated gold

Silver 8 to 20 µin

Immersion tin 30 to 70 µin

Organic surface protectant 0.4 to 0.6 µin

* Tab nickel/gold plating is applied using an electroplate process that results in a harder and thicker coating than the ENIG process. Tab nickel/gold is used only for areas of a circuit board that will be inserted into a connector.

Cost comparisons of various coating options are difficult since two of the metals (gold and silver) are sold by the troy ounce. However, for a typical board with approximately 15 percent exposed soldering surfaces the following table provides a good comparison, using HASL as the baseline.

Coating Cost Factor

HASL
1.00

ENIG
2.00

Silver
1.36

Immersion tin
1.30

Organic surface protectant
1.05

Cleanliness

DI water purity in the U.S. is measured with resistivity in megohm-centimeters, while Europe uses conductivity, which is the inverse.

The NaCl equivalent standard was developed to allow one test measurement to yield a value with a common meaning no matter what type of contaminant is present. The value is a calculation of the amount of NaCl that, if dissolved in the solution, would produce the same measured resistivity. The value does not mean there is necessarily any NaCl in the solution. dsi ’s standard for assemblies is less than 0.5μg/cm².

Controlled Impedance

dsi uses the following formula for calculating stripline impedance:

The stripline formula can be read as 60 divided by the square root of the dielectric constant multiplied by the natural log of (twice the dielectric space plus the trace thickness) divided by (the trace width multiplied by 0.8 plus the trace thickness) all multiplied by 1.9. Impedance formulas vary depending on impedance type, but calculations are similar.

dsi customer engineers verify the designers’ calculations of all controlled impedance boards before fabrication. As a service to customers, an impedance calculator is available on the dsi web site. Unlike most impedance calculators, the dsi calculator allows for normal process variables as well as theoretical computation.

SMT Process

IPC Class III requires that 75% of the lead must be on the pad. dsi validates the placement accuracy of each SMT line weekly and allows a maximum axis error of 1 mil (.001") and a true position error of 1.5 mils (.0015"). This will allow placement of a 12 mil pitch QFP to IPC Class III.

dsi has a DOE (Design of Experiments) test kit available with 48 boards imprinted with the test pattern, an evaluation worksheet, test instructions, and an Excel spreadsheet that can be used to correlate the data.

Test Methods

99% Final Test Yield means 1% of the boards go to rework.

90% First Pass Yield means 10% of the boards go to rework.

Therefore, 11% of the boards incur rework cost!

95% Test Effectiveness means 5% of the boards sent to the field could be defective.

80% Test Coverage means 20% of the boards cannot be tested.

20% of the circuitry multiplied by 10% (100% minus the 90% First Pass Yield) means that an additional 2% of the boards sent to the field could be defective.

Therefore, 7% of the boards sent to the field could be defective and incur warranty cost!

The acronym “DOE” is often used in place of Design of Experiments. DOE is a structured methodology for establishing process variability and capability by tabulating the data from successive passes through the process. Engineers use this data to determine whether the process can meet the customer’s requirements.

dsi uses AOI to inspect all SMT assemblies. On a typical day over 250,000 components are scanned for acceptance.

Resources and References
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