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Test Strategies for Improving Yield

dsi utilizes both conventional Time Domain Reflectometry (TDR) on a test coupon and flying probe technology to evaluate the actual traces of the circuit design. A test coupon alone is not adequate for high performance designs.

When fabricators receive board designs specified with controlled impedance, several key characteristics must be verified immediately to ensure manufacturing ease and high yields. Some of the major characteristics that must be determined are impedance type, feature size, dielectric material, copper weight, and test methods.

It is easy to say that adjustments can be made to account for tough designs. In reality, there are limits to every process; even when adjustments can be made, they incur additional costs that are eventually passed on to the customer. The goal should be to work through all variables initially so that a manufacturable and cost-effective board is produced. The customer must be involved on the front end with the issues that impact manufacturing to ensure that the board vendor delivers the best possible support, service, and quality.

While designers may employ various types of impedance, they may not be aware that some impedance designs are more difficult to manufacture than others. This brief example contrasts two similar impedance designs. Let us take a balanced embedded stripline (Figure 2.1) and compare it with an unbalanced or asymmetric stripline (Figure 2.2).

Balanced Stripline Design

The text box associated with Figure 2.1 lists critical details about the impedance design. This design is called a balanced stripline because the dielectric space between the two ground layers is equal.


Figure 2.1 Balanced Stripline Design

Balanced stripline designs absorb quite a bit of variability during manufacture. For example:

  • If the dielectric space varies by +/- 1 mil within a 0.015 to 0.017 range through the lamination cycle, this yields a 1.62 Ohm variation in impedance from the target value.


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  • If the trace width varies by +/-1 mil, the impedance value is affected by 1.74 Ohms.
dsi has developed a proprietary calculator, which is available on the rapidproto Web site. The process variables have been incorporated into this calculator to allow a designer to determine if a requested tolerance is practical.

The final value to consider is the dielectric constant (Dk) that is selected. The Dk of FR4 material ranges from 4.2 to 4.8. A prudent choice is the center of the window with a value of 4.5. For every tenth in variation of Dk, we can expect a 0.49 Ohm variation from the target. The sum of these values gives us the additive process variation inherent in this design.

In this case we have a process variation of 3.85 Ohms that is well within the 50 Ohms +/- 10 percent (+/- 5 Ohms). This design would be considered within normal processing means and would be simple to manufacture. The values listed above can be obtained by plugging the numbers, including the tolerances, into a balanced stripline impedance formula. Note that formulas listed in publications such as IPC-D-317A are approximations. Therefore, it is necessary to correlate the theoretical value with the output from a calculator based upon process variables.

Unbalanced Stripline Design

Now let’s look at a similar impedance design and compare it to the previous example. Figure 2.2 shows a similar design called an unbalanced or asymmetric stripline.


Figure 2.2 Unbalanced Stripline Design

This design is set up for an impedance target of 50 Ohms +/- 10 percent. This type of design is called an unbalanced stripline because the dielectric spaces on each side of the trace are not equal. Unbalanced impedance designs can present challenges to manufacturers if the critical variables are not accounted for up front. For example:

  • If the dielectric space H is allowed to vary +/- 1 mil, the trace will experience an impedance variation of 5.25 Ohms.


  • If the dielectric space H1 is allowed to vary +/- 1 mil, the trace impedance will vary only 0.26 Ohms.


  • The trace width is also allowed to vary +/- 1 mil for a 4.64 Ohm variation.


  • Finally, for every tenth the Dk varies, a 0.57 Ohm variation is observed.

If the variations are summed together, a processing tolerance of 10.72 Ohms is obtained. This tolerance is well beyond the 50 Ohms +/-10 percent (+/- 5 Ohms) specified by the customer. Table 1.1 below compares the process variations between the two stripline designs.

Table 1.1 Comparison between Process Variations

  Balanced Stripline Unbalanced Stripline
Dielectric Space (H) +/- .001 1.62 Ohms +/- .001 5.25 Ohms
Dielectric Space (H1) N/A N/A +/- .001 0.26 Ohms
Trace Width +/- .001 1.74 Ohms +/- .001 4.64 Ohms
Dielectric Constant +/- 0.1 0.49 Ohms +/- 0.1 0.57 Ohms
Total Variation   3.85 Ohms   10.72 Ohms

Armed with this data, the manufacturer can identify the most sensitive variables and apply tighter controls. In this case, dielectric space H is very sensitive while dielectric space H1 is not, leading to two manufacturing changes:

  1. The dielectric space H must be tightly controlled, and B stage combinations must be selected that will yield predictable thicknesses after lamination.


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  2. The trace width must also be held to tight controls during the inner layer stage.

These two changes in manufacturing will ensure a high yield and quality circuit board. By understanding this sensitivity up front, manufacturing difficulties can be avoided and a quality product can be delivered on time.

To summarize, impedance parameters must be understood before the fabrication process begins. The individual variables should be quantified so the proper strategy can be selected to ensure success during manufacturing. This article discusses the two most basic impedance types. In future articles, we will examine the manufacturing challenges presented by differential, coplanar, and dual stripline impedance designs.