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In the high-mix market served by dsi, the cost of a printed circuit board is based on the number of labor centers that are required to build the board and the time spent in each labor center. dsi employs activity-based costing and has divided the printed circuit board division into over 50 cost centers.

With activity-based costing, there are two facets to consider. The first consideration is machine, process, or area set-up that includes items such as loading drill bits or photo tools. This set-up cost is usually independent of the number of panels to be processed and is often a constant for non-mechanical operations such as exposing, plating or screening.

The second consideration is a variable run-time cost that changes based on the total quantity of panels to be processed within the work center. Most chemical processes require a constant time per panel. However, for mechanical processing such as drilling a high density board with a large number of vias, the run time swamps the set-up time. For example, it might take one hour to set up a CNC drill, but the run time for a multi-panel job with one hole might be the same as a single panel job with a thousand holes. The cost of the job within the work center is the sum of the set-up time and the process time, all multiplied by the cost per minute for the work center. It is very important to understand that printed circuit boards are produced in a "manufacturing panel" and that the actual costing is based on the cost to produce the panel. The individual board price is derived by dividing the panel cost by the number of printed circuit boards that are contained within the panel.

The following characteristics can affect the cost of your circuit board.

Bare Board Dimensions, Type and Material Odd (instead of even) dimensions yield a higher number of boards per panel to decrease costs. Using double-sided boards as the baseline, multi-layer boards do not automatically double in price as you add layers: Number of Layers Cost Factor Single-sided x 0.67 Double-sided 1.0 (base factor) 4-layer x 1.75 6-layer x 2.25 8-layer x 3.00 10-layer x 3.50 12-layer x 4.25 14-layer x 5.25 Lead-free Fr4 boards have no additional processing costs but do have an increased cost due to increased raw laminate costs and choice of alternative final finish (lead-free HASL, electroless nickel/immersion gold, immersion silver, immersion tin, organic coating). If spacing between solderable features is <.006", there is an increased potential for HASL shorts and reduced yields. Alternative finishes are recommended to improve overall yields. Immersion silver and immersion tin are more cost effective surface finishes than electroless nickel/immersion gold due to lower metal costs and shorter dwell times.

Surface Finishes If spacing between solderable features is <.006", there is an increased potential for HASL shorts and reduced yields. Alternative finishes are recommended to improve overall yields. Immersion silver and immersion tin are more cost effective surface finishes than electroless nickel/immersion gold due to lower metal costs and shorter dwell times.

Multi-layer Constructions with "Cap" Builds, Overly Specified Builds or Thin Thickness A "cap" build instead of a "foil" build increases the number of material cores and processing costs. Example A 4-layer cap build uses 2 cores with processing costs of a 6-layer foil build.   A 4-layer foil build uses 1 core with standard 4-layer processing costs. Requesting very specific builds, cores, prepreg, and so forth can increase cost if the materials are not stocked. A high layer count and a board thickness less than .062" can increase both material and handling costs for thinner cores.

Hole Size and Aspect Ratio An aspect ratio greater than 6:1 reduces drilling stack height and hit count per drill bit. Smaller holes increase processing costs for electroless and pattern plating.

Trace and Space Widths Trace and space widths less than .006" increase manufacturing costs. Tight trace width tolerances in combination with increased copper thickness can increase etching and dry film stripping processing.

Other Considerations Extremely tight tolerances for traces, spaces, hole size, registration, and controlled impedance. Reduced manufacturing annular ring (pad size to finished hole size less than .0085") increases drilling and registration difficulty. Conductive filled via costs may be 2x greater than non-conductive filled vias. Bare copper is a better conductor, so consider increasing copper thickness in combination with non-conductive via filling for a more cost efficient and effective design. Carbon ink patterns oriented in multiple directions may require multiple set-ups and processing if carbon pad overlap per side of copper pad is <.007" or if adjacent features have <.015" spacing. Expect an increase in both board and tooling costs. High layer counts with high inner layer copper requirements increase drilling costs. Use of tight surface mount pitch parts, less than .020", (with soldermask dams more or less than .003") can increase soldermask screening costs. Arrays designed with a high number of boards per array and no x-outs increases the manufacturing scrap factor.

Blind/Buried Vias and Sequential Lamination Blind vias require depth drilling, which leads to additional programming, drill set-ups, and set-up materials. Each additional blind via drill file requires additional programming and drill set-ups. Expect an increase in board costs and tooling costs. Blind vias designed from the "outside in" (instead of the "inside out") require sequential lamination, which adds extra set ups and run times for drilling, pattern plating and multi-layer pressing. Example: An 8-layer board with blind vias on Layer 1-2, Layer 1-4, and Layer 1-6 would require three additional set ups. Conductive filled via costs may be 2x greater than non-conductive filled vias. Bare copper is a better conductor, so consider increasing copper thickness in combination with non-conductive via filling for a more cost efficient and effective design. Buried vias (plated through-holes on inner layers) require sequential lamination with extra drilling, pattern plating and multi-layer pressing for each blind via layer.